Configuring IOP/Core Interaction
2-6 ADSP-21368 SHARC Processor Hardware Reference
In order to resolve this issue, use one of the following methods.
1. Read an IOP register from the same peripheral block before execut-
ing the RTI. This read forces the write to occur first.
dm(TXSPI) = R0; /* Write to TXSPI FIFO */
R0 = dm(SPICTL); /* Dummy read. This read happens only
after write */
rti;
2. Add sufficient NOP instructions after a write. In all cases, ten NOP
instructions after a write is sufficient to properly update the status.
R0 = 0x0;
dm(SPICTL) = R0; /* Disable spi */
nop; nop; nop; nop; nop;
nop; nop; nop; nop; nop;
rti;
Configuring IOP/Core Interaction
There are two methods the processor uses to monitor the progress of
DMA operations—interrupts, which are the primary method, and status
polling. The same program can use either method for each DMA channel.
The following sections describe both methods in detail.
Interrupt-Driven I/O
Interrupts are generated at the end of a DMA transfer. This happens when
the count register for a particular channel decrements to zero. The default
interrupt vector locations for each of the channels are listed in Table 2-3
on page 2-9. The interrupt register diagrams and bit descriptions are given
in Appendix B, Interrupts and “DAI Interrupt Controller Registers” on
page A-112.
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