ADSP-21368 SHARC Processor Hardware Reference 2-7
I/O Processor
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The processors also have programmable interrupts using the
peripheral interrupt priority control registers, PICRx. For more
information, see “Peripheral Interrupt Priority Control Registers”
on page A-164.
Programs can check the appropriate status or configuration register to
determine which channels are performing a DMA or chained DMA.
All DMA channels can be active or inactive. If a channel is active, a DMA
is in progress on that channel. The I/O processor indicates the active sta-
tus by setting the channel’s bit in the status register. The only exception to
this is the IDP_DMAx_STAT bits of the DAI_STAT register can become active
even if DMA, through some IDP channel, is not intended.
The following are some other I/O processor interrupt attributes.
• When an unchained (single block) DMA process reaches comple-
tion (as the count decrements to zero) on any DMA channel, the
I/O processor latches that DMA channel’s interrupt. It does this by
setting the DMA channel’s interrupt latch bit in the IRPTL, LIRPTL,
DAI_IRPTL_H, or DAI_IRPTL_L registers.
• For chained DMA, the I/O processor generates interrupts in one of
two ways:
If PCI = 1, bit 19 of the chain pointer register is the program con-
trolled interrupts bit and an interrupt occurs for each DMA in the
chain.
If PCI = 0, an interrupt occurs at the end of a complete chain. (For
more information on DMA chaining, see “DMA Controller Oper-
ation” on page 2-13.)
• When a DMA channel’s buffer is not being used for a DMA pro-
cess, the I/O processor can generate an interrupt on single word
writes or reads of the buffer. This interrupt service differs slightly
for each port. For more information on single-word inter-
rupt-driven transfers, see “Serial Port Control Registers (SPCTLx)”
on page 5-59.
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