Configuring IOP/Core Interaction
2-8 ADSP-21368 SHARC Processor Hardware Reference
During interrupt-driven DMA, programs use the interrupt mask bits in
the
IMASK, LIRPTL, DAI_IRPTL_PRI, DAI_IRPTL_RE, and DAI_IRPTL_FE reg-
isters to selectively mask DMA channel interrupts that the I/O processor
latches into the IRPTL, LIRPTL, DAI_IRPTL_H, and DAI_IRPTL_L registers.
L
The I/O processor only generates a DMA complete interrupt when
the channel’s count register decrements to zero as a result of actual
DMA transfers. Writing zero to a count register does not generate
the interrupt. To stop a DMA preemptively, write a one to the
count register. This causes one more word to be transferred or
received and an interrupt is then generated.
A channel interrupt mask in the IMASK, LIRPTL, DAI_IRPTL_PRI,
DAI_IRPTL_RE, and DAI_IRPTL_FE registers determines whether a latched
interrupt is to be serviced or not. When an interrupt is masked, it is
latched but not serviced. For more information on the IMASK and LIRPTL
registers, see “Interrupt Registers” on page B-6.
L
By clearing a channel’s PCI bit during chained DMA, programs
mask the DMA complete interrupt for a DMA process within a
chained DMA sequence.
The I/O processor can also generate interrupts for I/O port operations
that do not use DMA. In this case, the I/O processor generates an inter-
rupt when data becomes available at the receive buffer or when the
transmit buffer is not full (when there is room for the core to write to the
buffer). Generating interrupts in this manner lets programs implement
interrupt-driven I/O under control of the processor core. Care is needed
because multiple interrupts can occur if several I/O ports transmit or
receive data in the same cycle.
The digital audio interface (DAI) has two interrupts—the lower priority
option (
DAILI) and higher priority option (DAIHI). This allows two inter-
rupts to have priorities that are higher and lower than serial ports.
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