Structure of the Interfaces
4-2 ADSP-21368 SHARC Processor Hardware Reference
The following sections describe the general operating theory of both the
DAI and DPI as well as their SRUs.
Structure of the Interfaces
Both the DAI and DPI incorporate a specific set of peripherals and a very
flexible routing (connection) system permitting a large combination of
signal flows. A set of DAI/DPI-specific registers make such design, con-
nectivity, and functionality variations possible. All routing related to
peripheral states for the DAI/DPI interfaces are specified using registers
related to each interface. For more information on pin states, refer to
Figure 4-6 on page 4-10.
The DAI/DPI may be used to connect any combination of inputs to any
combination of outputs. This function is performed by the SRUs through
memory-mapped registers.
Input Data Port Flags (12)
General-Purpose I/O (20 channels)
1 The precision clock generator (PCG) units C and D can also be routed through
the DPI.
2 SPORT6 and SPORT7 receive clocks from other sources but cannot send their
own clocks to other SPORTS or other peripherals internally through SRU1. If
needed, they have to be connected externally through pins.
Table 4-1. Signal Routing Unit Peripheral Assignments (Cont’d)
DAI SRU1 DPI SRU2
1
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