ADSP-21368 SHARC Processor Hardware Reference 13-13
Precision Clock Generators
Bypass mode also enables the generation of a strobe pulse (one-shot).
Strobe usage ignores the counter and looks to SRU1 to provide the input
signal.
Bypass as a One-Shot
When the
STROBEA or STROBEB bits (bit 0, bit 16 of the PCG_PW register) or
STROBEC or STROBED bits (bit 0, bit 16 of the PCG_PW2 register) are set (= 1),
the one-shot option is used. When the STROBEx bit is set (= 1), the frame
sync is a pulse with a duration equal to one period, or one full cycle of
MISCA2_I for unit A, MISCA3_I for unit B, MISCA4_I for unit C, and
MISCA5_I for unit D that repeats at the beginning of every clock input
period. This pulse is generated during the high period of the input clock
when the INVFSA/B/C/D bits (bits 1 or 17, respectively of the PCG_PW and
PCG_PW2 registers) are cleared (INVFSA/B=0) or during the low period of the
input clock when invert bits INVFSA/B/C/D are set (= 1).
A strobe period is equal to the period of the normal clock input signal spec-
ified by the FSASOURCE bit (bit 30 in the PCG_CTLA1 register for unit A) and
the corresponding FSxSOURCE bit (bit 30 in the PCG_CTLx1 registers for
units B, C, and D).
As shown in Figure 13-5, the output pulse width is equal to the period of
the SRU1 source signal (MISCA2_I for frame sync A, MISCA3_I for frame
sync B, MISCA4_I for frame sync C, and MISCA5_I, for frame sync D). The
pulse begins at the second rising edge of
MISCAx_I following a rising edge
of the clock input. When the INVFSA/B/C/D bit is set, the pulse begins at
the second rising edge of
MISCAx_I, coincident or following a falling edge
of the clock input.
For more information, see “Group E Connections—Interrupts and Mis-
cellaneous Signals” on page 4-43.
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