ADSP-21368 SHARC Processor Hardware Reference 12-17
Two Wire Interface Controller
Master Mode Clock Setup
Master mode operation is set up and executed on a per-transfer basis. An
example of programming steps for a receive and for a transmit are given
separately in following sections. The clock setup programming step listed
here is common to both transfer types.
Program the TWIDIV register. This defines the clock high duration and
clock low duration.
Master Mode Transmit
Follow these programming steps for a single master mode transmit:
1. Program the TWIMADDR register. This defines the address transmit-
ted during the address phase of the transfer.
2. Program the TXTWI8 or TXTWI16 registers. This is the initial data
transmitted. It is considered an error to complete the address phase
of the transfer and not have data available in the transmit FIFO
buffer.
3. Program the TWIFIFOCTL register. Indicate if transmit FIFO buffer
interrupts should occur with each byte transmitted (8 bits) or with
each 2 bytes transmitted (16 bits).
4. Program the
TWIIMASK register. Enable bits associated with the
desired interrupt sources. As an example, programming the value
0x0030 results in an interrupt output to the processor in the event
that the master transfer completes, or if the master transfer has an
error.
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