ADSP-21368 SHARC Processor Hardware Reference 14-1
14 SYSTEM DESIGN
The ADSP-21367/8/9 and ADSP-2137x processors support many system
design options. The options implemented in a system are influenced by
cost, performance, and system requirements. This chapter provides the
following system design information:
• “Processor Pin Descriptions” on page 14-2
• “Clock Derivation” on page 14-13. Includes “Power Management
Control Register”, “Phase-Locked Loop Startup”, “RESET and
CLKIN”.
• “Conditioning Input Signals” on page 14-32
• “Designing for High Frequency Operation” on page 14-33
• “Booting” on page 14-37
• “Data Delays, Latencies, and Throughput” on page 14-52
Other chapters also discuss system design issues. Some other locations for
system design information include:
• “SPORT Operation Modes” on page 5-10
• “SPI General Operations” on page 6-8
By following the guidelines described in this chapter, you can ease the
design process for your ADSP-21367/8/9 and ADSP-2137x processor
product. Development and testing of your application code and hardware
can begin without debugging the debug port.
To Next Page
Loading...
Need help?
General
