Electrical Specifications
12-22 ADSP-21368 SHARC Processor Hardware Reference
•
TWIMCOMP interrupt
This interrupt has occurred due to the completion of the data
receive transfer. At this time the data transmit transfer begins. The
TWIDCNT field should be set to reflect the number of bytes to be
transmitted. Clear the TWIRSTART bit if this is the last transfer.
• TWITXINT interrupt
This interrupt is generated when there is one or two bytes of empty
space in the FIFO. Simple data handling is all that is required.
• TWIMCOM interrupt
The transfer is complete.
Electrical Specifications
All logic complies with the electrical specification outlined in the Philips
I
2
C Bus Specification version 2.1 dated January, 2000.
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