ADSP-21368 SHARC Processor Hardware Reference 11-9
UART Port Controller
For information on using the UART for DMA transfers, see “UART
DMA” on page 2-44, “DAI/DPI Interrupt Controller” on page 4-65, and
“Peripheral Interrupt Priority Control Registers” on page A-164.
L
Even though the UART has two interrupts for receive and trans-
mit, in I/O mode, all interrupts are grouped as a single receive
interrupt.
The UARTLSIE bit (bit 2) enables interrupt generation on an independent
interrupt channel when any of the following conditions are raised by the
respective bit in the UART line status register (UARTxLSR):
• Receive overrun error (UARTOE)
• Receive parity error (UARTPE)
• Receive framing error (UARTFE)
• Break interrupt (UARTBI)
When the UARTTBEIE bit is set in the UARTxIER register in I/O mode, the
UART module immediately issues an interrupt. When initiating the trans-
mission of a string, no special handling of the first character is required.
Set the UARTTBEIE bit (bit 1) and let the interrupt service routine (ISR)
load the first character from memory and write it to the UARTxTHR register
in the normal manner. Accordingly, the UARTTBEIE bit should be cleared if
the string transmission has completed.
UARTxIIR Register
For legacy reasons, the UART interrupt identification register (UARTxIIR)
still reflects the UART interrupt status (see Table 11-1). Legacy operation
may require bundling all UART interrupt sources to a single interrupt
channel and servicing them all by the same software routine. This can be
established by globally assigning all UART interrupts to the same
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