Analog Devices SHARC ADSP-21368

External Port Registers
A-14 ADSP-21368 SHARC Processor Hardware Reference
External Port DMA Control Registers (DMACx)
The DMAC0–1 registers control the DMA function of their respective DMA
channels. These registers are shown in Figure A-5 and described in
Table A-4.
Figure A-5. External Port DMA Registers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAEN
EXTS
TLS
Tap List Loading Status (RO)
1=Loading active
0=Loading inactive
DMAS
DMA Transfer Status (RO)
0=DMA idle
1=DMA in progress
DMADR
DMA Direction
0 = Write to internal memory
(external reads)
1 = Read from Internal memory
(external writes)
DMA Enable
1=Enable
0=Disable
CHEN
Chaining Enable
1=Enable
0=Disable
DFS
DMA FIFO Status (RO)
00=FIFO empty, 01=FIFO partially full
11=FIFO full, 10=Reserved
TFS
Tap List FIFO Status (RO)
00=FIFO empty, 01=FIFO partially full
11=FIFO full, 10=Reserved
DMAC0 (0x180B)
DMAC1 (0x180C)
31 30 29 28 27 26 24 23 22 21 20 19 18 17 16
0000000000000000
DIRS
Reserved
25
DLEN
Delay Line DMA Enable
1=Enable
0=Disable
CBEN
Circular Buffering Enable
1=Enable
0=Disable
DFLSH
Flush DMA FIFO (WO)
TFLSH
Flush Tap List FIFO (WO)
CHS
DMA Chaining Status (RO)
1=DMA in progress
0=DMA Idle
DMA Transfer Direction Status
1=Direction is external writes
0=Direction is external reads
0000000000000000
WBS
Delay Line Write Back Status (RO)
1=Write back is active
0=Write back is not active
DMA External Interface
Status (RO)
1=Access pending
0=No access pending