ADSP-21368 SHARC Processor Hardware Reference 3-73
External Port
Changing System Clock During Runtime
All timing specifications are normalized to the system clock. Since most of
these are minimum specifications, (except t
REF
, which is a maximum spec-
ification), a variation of the system clock violates a specific specification
and causes a performance degradation for the other specifications.
The reduction of system clock violates the minimum specifications, while
increasing the system clock violates the maximum t
REF
specification.
Therefore, careful software control is required to adapt these changes.
L
For most applications, the SDRAM power-up sequence and writ-
ing of the mode register needs to occur only once. Once the
power-up sequence has completed, the SDPSS bit should not be set
again unless a change to the mode register is desired.
The recommended procedure for changing the system frequency
SDCLK is as follows.
1. Set the SDRAM to self-refresh mode by writing a 1 to the
SDSRF bit of SDCTL register.
2. Poll the SDSRA bit of SDSTAT register for self-refresh grant.
3. Execute the desired PLL programming sequence. (For
details see “PLL Programming Examples” on page 14-16).
4. Wait until the signal RESETOUT/CLKOUT is asserted which
ensures that the PLL has settled to the new frequency.
5. Reprogram the SDRAM registers (
SDRRC, SDCTL) with values
appropriate to the new SDCLK frequency and assure that the
SDSRF bit is set.
6. Bring the SDRAM out of self-refresh mode by performing a
read or write access.
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