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ADSP-21368 SHARC Processor Hardware Reference 9-13

S/PDIF Transmitter/Receiver

Standalone Mode

This mode is selected by setting bit 9 in the

DITCTL register. In this mode,

the block start bit (indicating start of a frame) is generated internally. The

channel status bits come from the channel status buffer registers (DITCHA-

NAx and DITCHANBx). The user status bits come from the user bits buffers

(DITUSRBITAx and DITUSRBITBx). The channel status buffer must be pro-

grammed before the SPDIF transmitter is enabled and used for all the

successive blocks of data.

Once the user bits buffer registers (DITUSRBITA0-5 and DITUSRBITB0-5) are

programmed, they are used only for the next block of data. This allows

programs to change the user bit information in every block of data. After

writing to the required user bit buffer registers to change the user bits for

the next block, these registers must be rewritten to enable the use of these

bits in the next block. The validity bit for channel A and B are taken from

bit 10 and bit 11 of the DITCTL register. In this mode only audio data

comes from the SDATA pin. All other data, including the status bit and

block start bit is either generated internally or taken from the internal

Full Serial Mode

This mode is selected by clearing bit 9 in the DITCTL register. In this mode

all the status bits, audio data and the block start bit (indicating start of a

frame), come through the SDATA pin. The transmitter should be enabled

after or at the same time as all of the other control bits.

Analog Devices SHARC ADSP-21368 User Manual

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