Analog Devices SHARC ADSP-21368 User Manual

ADSP-21368 SHARC Processor Hardware Reference A-145
Register Reference
FIFO Status Register (TWIFIFOSTAT)
The fields in the TWI FIFO status register (TWIFIFOSTAT, shown in
Figure A-66 and described in Table A-60) indicate the state of the FIFO
buffers’ receive and transmit contents. The FIFO buffers do not discrimi-
nate between master data and slave data. By using the status and control
bits provided, the FIFO can be managed to allow simultaneous master and
slave operation. All bits in this register are read-only.
Figure A-66. FIFO Status Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
TWITXS
TWIRXS
TWIFIFOSTAT (0x442C)
Receive FIFO Status
00=FIFO is empty
01=FIFO contains one byte of data
11=FIFO is full and contains two bytes of data
10=Illegal
Transmit FIFO Status
00=FIFO is empty
01=FIFO contains one byte of data
11=FIFO is full and contains two
bytes of data
10=Illegal

Analog Devices SHARC ADSP-21368 Specifications

General

Brand	Analog Devices
Model	SHARC ADSP-21368
Category	Computer Hardware
Language	English