ADSP-21368 SHARC Processor Hardware Reference A-135
Register Reference
Slave Address Register (TWISADDR)
The TWI slave mode address register (TWISADDR, shown in Figure A-60)
holds the slave mode address, which is the valid address that the
slave-enabled TWI controller responds to. The TWI controller compares
this value with the received address during the addressing phase of a
transfer.
Slave Status Register (TWISSTAT)
During and at the conclusion of slave mode transfers, the TWI slave mode
status register (TWISSTAT, shown in Figure A-61) holds information on the
current transfer. Generally slave mode status bits are not associated with
the generation of interrupts. Master mode operation does not affect the
slave mode status bits.
Figure A-60. Slave Mode Address Register
Figure A-61. Slave Mode Status Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
SADDR
TWISADDR (0x4410)
Slave Mode Address
Valid address which this slave enabled
TWIC Master responds to
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Reset = 0x0000
TWISSTAT (0x440C)
TWISDIR Slave Transfer
Direction
TWIGC (General Call)
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