ADSP-21368 SHARC Processor Hardware Reference 7-11
Input Data Port
Packing Mode 01
Mode 01 packs three acquired samples together. Since the resulting 32-bit
word is not divisible by three, up to 10 bits are acquired on the first clock
edge and up to 11 bits are acquired on each of the second and third clock
edges:
• On clock edge 1, bits 19–10 are moved to bits 9–0 (10 bits)
• On clock edge 2, bits 19–9 are moved to bits 20–10 (11 bits)
• On clock edge 3, bits 19–9 are moved to bits 31–21 (11 bits)
This mode sends one packed 32-bit word to FIFO for every three input
clock cycles—the DMA transfer rate is one-third the PDAP input clock
rate.
Packing Mode 00
Mode 00 moves data in four cycles. Each input word can be up to 8 bits
wide.
• On clock edge 1, bits 19–12 are moved to bits 7–0
• On clock edge 2, bits 19–12 are moved to bits 15–8
• On clock edge 3, bits 19–12 are moved to bits 23–16
• On clock edge 4, bits 19–12 are moved to bits 31–24
This mode sends one packed 32-bit word to FIFO for every four input
clock cycles—the DMA transfer rate is one-quarter the PDAP input clock
rate.
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