ADSP-21368 SHARC Processor Hardware Reference A-51
Register Reference
SPORT DMA Count Registers (CSPx)
The CSPx registers are 16 bits wide and they hold the word count for a
DMA transfer. For more information, see “I/O Processor” on page 2-1
The reset value for these registers is undefined. The addresses of the CSPx
registers are:
SPORT Chain Pointer Registers (CPSPx)
The CPSPx registers are 20 bits wide. They hold the address for the next
transfer control block in a chained DMA operation. For more informa-
tion, see “I/O Processor” on page 2-1. The reset value for these registers is
undefined. The addresses of the CPSPx registers are:
CSP0A – 0xC42 CSP0B – 0xC46
CSP1A – 0xC4A CSP1B – 0xC4E
CSP2A – 0x442 CSP2B – 0x446
CSP3A – 0x44A CSP3B – 0x44E
CSP4A – 0x842 CSP4B – 0x846
CSP5A – 0x84A CSP5B – 0x84E
CSP6A – 0x4842 CSP6B – 0x4846
CSP7A – 0x484A CSP7B – 0x484E
CPSP0A – 0xC43 CPSP0B – 0xC47
CPSP1A – 0xC4B CPSP1B – 0xC4F
CPSP2A – 0x443 CPSP2B – 0x447
CPSP3A – 0x44B CPSP3B – 0x44F
CPSP4A – 0x843 CPSP4B – 0x847
CPSP5A – 0x84B CPSP5B – 0x84F
CPSP6A – 0x4843 CPSP6B – 0x4847
CPSP7A – 0x484B CPSP7B – 0x484F
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