ADSP-21368 SHARC Processor Hardware Reference 3-91
External Port
/* Force an auto-refresh */
ustat1 = dm(SDCTL);
bit set ustat1 F_AR;
dm(SDCTL) = ustat1;
After this code is executed, the processors in the system can start
normal external accesses. These steps must be repeated when a pro-
cessor is reset.
Bus Synchronization Notes
1. During normal operation, do not reset the current bus master
(external hard reset) as this causes system synchronization prob-
lems. A few key signals (for example SDCLK) are three stated or
undriven at reset.
2. The SDCLK and CLKIN signals are used in the arbitration logic for
the shared external bus. This logic requires that these clocks are ris-
ing edge aligned to function properly. Therefore, not all clock
ratios are allowed in shared memory systems. The values of PLLM
(PLL multiplier) and PLLD (PLL divider), which are set in the
power management control register (PMCTL), need to be pro-
grammed such that the ratio (PLLM/2PLLD) is an integer. For
more information, see “Power Management Control Register
(PMCTL)” on page A-170.
3. If the clock ratio from the PLL is changed by programming values
of PLLM and/or PLLD in the
PMCTL register, the FSYNC bit (bit 28
of SYSCTL register) should be set to re synchronize the shared mem-
ory system. This bit should be cleared after meeting the PLL
settling time and the clock locks to the new ratio. If only the value
of PLLD is programmed, in addition to the above, enter dummy
bypass mode by setting and clearing the
PLLBP bit (bit 15 in the
PMCTL register) to ensure the SDCLK and CLKIN are rising edge
aligned.
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