ADSP-21368 SHARC Processor Hardware Reference 5-13
Serial Ports
Standard DSP Serial Mode Control Bits
Several bits in the
SPCTLx control register enable and configure standard
DSP serial mode operation:
• Operation mode, master mode enable (OPMODE)
• Word length (SLEN)
• SPORT enable (SPEN_A and SPEN_B)
Clocking Options
In standard DSP serial mode, the SPORTs can either accept an external
serial clock or generate it internally. The ICLK bit in the SPCTL register
determines the selection of these options (see “Clock Signal Options” on
page 5-36 for more details). For internally-generated serial clocks, the
CLKDIV bits in the DIVx register configure the serial clock rate (see
Figure 5-10 on page 5-70 for more details).
Finally, programs can select whether the serial clock edge is used for sam-
pling or driving serial data and/or frame syncs. This selection is performed
using the CKRE bit in the SPCTL register (see Table A-8 on page A-37 for
more details).
Frame Sync Options
A variety of framing options are available for the SPORTs. For detailed
descriptions of framing options, see “Frame Sync Options” on page 5-37.
In this mode, these options are independent of clocking, data formatting,
or other configurations. The frame sync signal (
SPORTx_FS) is used as a
framing signal for serial word transfers.
Framing is optional for serial communications. The FSR bit in the SPCTL
register controls whether the frame sync signal is required for every serial
word transfer or if it is used simply to start a block of serial word transfers.
See “Framed Versus Unframed Frame Syncs” on page 5-37 for more
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