ADSP-21368 SHARC Processor Hardware Reference 5-75
Serial Ports
Although the DMA transfers are performed with 32-bit words, SPORTs
can handle word sizes from 3 to 32 bits, with 8 to 32 bits for I
2
S mode. If
serial words are 16 bits or smaller, they can be packed into 32-bit words
for each DMA transfer. DMA transfers are configured using the PACK bit
in the SPCTLx registers. When SPORT data packing is enabled (PACK = 1),
the transmit and receive interrupts are generated for the 32-bit packed
words, not for each 16-bit word.
The following sections present an overview of SPORT DMA operations;
additional details are covered in the “Memory” chapter in the
ADSP-2136x SHARC Processor Programming Reference.
• For information on SPORT DMA channel setup, see “Setting Up
DMA on SPORT Channels” on page 5-75.
• For information on SPORT DMA parameter registers, see
“SPORT DMA Parameter Registers” on page 5-76.
• For information on SPORT DMA chaining, see “SPORT DMA
Chaining” on page 5-81.
Setting Up DMA on SPORT Channels
Each SPORT DMA channel has an enable bit (SDEN_A and SDEN_B) in its
SPCTLx registers. When DMA is disabled for a particular channel, the
SPORT generates an interrupt every time it receives a data word or when-
ever there is a vacancy in the transmit buffer. For more information, see
“Single Word Transfers” on page 5-81.
Each channel also has a DMA chaining enable bit (
SCHEN_A and SCHEN_B)
in its SPCTLx registers.
To set up a SPORT DMA channel, write a set of memory buffer parame-
ters to the SPORT DMA parameter registers as shown in Table 5-12.
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