ADSP-21368 SHARC Processor Hardware Reference 5-29
Serial Ports
After the
TXSPxA transmit buffer is loaded, transmission begins and the
SPORTx_TDV signal is generated. When SPORT DMA is used, this signal
may occur several cycles after the multichannel transmission is enabled. If
a deterministic start time is required, pre-load the transmit buffer.
Active State Multichannel Frame Sync Select
The LFS bit in the SPCTLx, registers selects the logic level of the multichan-
nel frame sync signals as active low (inverted) if set (=1), or active high if
cleared (=0). Active high (=0) is the default.
Multichannel Mode Control Bits
Several bits in the SPCTLx control register enable and configure multichan-
nel mode operation:
• Operation mode (OPMODE)
• Word length (SLEN)
• SPORT transmit/receive enable (SDEN_A and SDEN_B)
• Master mode enable (MSTR)
L
If the MCEA or MCEB bits are set (=1) in the SPMCTLx register, the
SPEN_A and SPEN_B bits in the SPCTL register must be cleared (=0).
The
SPCTLx control registers contain several bits that enable and configure
multichannel operations. Refer to Table 5-9 on page 5-59.
Multichannel mode is enabled by setting the MCEA or MCEB bit in the
SPMCTL0 through SPMCTL7 control register:
• When the
MCEA or MCEB bits are set (=1), multichannel operation is
enabled.
• When the
MCEA or MCEB bits are cleared (=0), all multichannel oper-
ations are disabled.
To Next Page
Loading...
