SPORT Operation Modes
5-30 ADSP-21368 SHARC Processor Hardware Reference
Multichannel operation is activated three serial clock cycles after the
MCEA/MCEB bits are set. Internally-generated frame sync signals activate four
serial clock cycles after the MCEA/MCEB bits are set.
Select the number of channels used in multichannel operation by using
the 7-bit NCH field in the multichannel control register. Set NCH to the
actual number of channels minus one:
NCH = Number of channels – 1
The 7-bit CHNL field in the multichannel control registers indicates the
channel that is currently selected during multichannel operation. This
field is a read-only status indicator. The CHNL(6:0) bits increment modulo
NCH(6:0) as each channel is serviced.
The 4-bit MFD field (bits 4-1) in the multichannel control registers
(SPMCTL0–7) specifies a delay between the frame sync pulse and the first
data bit in multichannel mode. The value of MFD is the number of serial
clock cycles of the delay. Multichannel frame delay allows the processor to
work with different types of telephony interface devices.
A value of zero for MFD causes the frame sync to be concurrent with the
first data bit. The maximum value allowed for MFD is 15. A new frame sync
may occur before data from the last frame has been received, because
blocks of data occur back-to-back.
Multichannel Frame Sync Source
Bit 14 (IMFS) in the SPCTLx registers selects whether the SPORT uses an
internally-generated frame sync (if set, =1) or frame sync from an external
(if cleared, =0) source.
Multichannel Status Bits
Bits 29 and 26 (
DERR_A and DERR_B) in the SPCTLx registers provide error
status information for the SPORT A and B channels. When the SPORT is
configured as a receiver this bit indicates the receiver overflow condition.
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