Memory-to-Memory DMA Register
A-28 ADSP-21368 SHARC Processor Hardware Reference
Memory-to-Memory DMA Register
The memory-to-memory (MTM) DMA register (MTMCTL) allows programs
to transfer blocks of 64-bit data from one internal memory location to
another. This transfer method uses two DMA channels, one for reading
data and one for writing data. These transfers are controlled using the
MTMCTL register shown in Figure A-12. For more information, see “Mem-
ory-to-Memory DMA” on page 2-48.
Figure A-12. MTM DMA Register (MTMCTL)
31 30 29 28 27 26 24 23 22 21 20 19 18 17 16
0000000000000000
Read of bits 29–4
returns 0
15 14 13 12 11 10 8 7 6 5 4 3 2 1 0
0000011110000000
MTMDMA0ACT
MTMDEN
MTM DMA Enable
1=Enable
0=Disable
Reserved
Memory Write DMA Status
MTMFLUSH
1=Flush the FIFO and reset the
read/write pointers
24
9
MTMCTL (0x2C01)
MTMDMA1ACT
Memory Read DMA Status
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