Configuring IOP/Core Interaction
2-16 ADSP-21368 SHARC Processor Hardware Reference
processor’s internal memory before it is used by the I/O processor. On the
ADSP-21367/8/9 and ADSP-2137x processors, this offset value is
0x0008 0000.
Bit 19 of the chain pointer register is the program-controlled interrupts
(
PCI) bit. This bit controls whether an interrupt is latched after every
DMA in the chain (when set), or whether the interrupt is latched after the
entire DMA sequence completes (if cleared).
L
The PCI bit only effects DMA channels that have chaining enabled.
Also, interrupt requests enabled by the PCI bit are maskable with
the IMASK register.
Because the PCI bit is not part of the memory address in the chain pointer
register, programs must use care when writing and reading addresses to
and from the register. To prevent errors, programs should mask out the
PCI bit (bit 19) when copying the address in a chain pointer register to
another address register.
The DMA registers are shown in Figure 2-1.
Transfer Control Block Chain Loading (TCB)
During TCB chain loading, the I/O processor loads the DMA channel
parameter registers with values retrieved from internal memory. The
address in the chain pointer register points to the highest address of the
TCB (containing the index parameter). This means that if a program
declares an array to hold the TCB, the chain pointer register should not
point to the first location of the array.
Table 2-4 shows the TCB-to-register loading sequence for the serial port
and SPI port DMA channels. The I/O processor reads each word of the
TCB and loads it into the corresponding register. Programs must set up
the TCB in memory in the order shown in Table 2-4, placing the index
parameter at the address pointed to by the chain pointer register of the
To Next Page
Loading...
Need help?
General
