ADSP-21368 SHARC Processor Hardware Reference 3-9
External Port
Instruction Storage and Packing
The ADSP-2137x processors incorporate a 32-bit SDRAM controller.
However, the SDRAM controller supports SDRAMs with data bus widths
of 16 as well as 32 bits. The packing logic in the SDRAM controller packs
the data from SDRAM into 48-bit instructions. Any address produced by
the sequencer which falls in external memory is first translated into the
physical address in external memory based on the actual data bus width of
external memory as shown in Figure 3-3.
The controller completes the required number of accesses from consecu-
tive locations for returning a 48-bit word instructions. For a 16-bit
SDRAM bus, it performs three accesses. For 32-bit SDRAM, three
accesses are performed for two instructions. In this packing mode, all the
even addresses in external memory are translated by multiplying the
address by a factor of 3/2. For example, if A is an even address falling in
external memory region (A > 0x200000), the translated address is
((A>>1) + A). For an odd address, the translated address for the previous
even address is incremented by 1. Note that it is the absolute address
rather than the offset from the base of external memory that is translated.
Therefore, the beginning of external memory, 0x200000, is translated to
0x300000. Two 32-bit accesses are performed for each even address. For
an odd address in the sequence, only one access is necessary. Two accesses
are necessary however, if the odd address happens to be first in a sequence.
L
Only bank0 can be populated for external code execution on
ADSP-2137x processors.
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