ADSP-21368 SHARC Processor Hardware Reference 3-63
External Port
• Select and enable the start of the SDRAM power-up sequence
(
SDPM, SDPSS)
• Select the column/row address widths
Once the SDPSS bit in the SDCTL register is set to 1, and a transfer occurs to
enabled SDRAM address space, the SDC initiates the SDRAM power-up
sequence. The exact sequence is determined by the SDPM bit in the SDCTL
register. The transfer that is used to trigger the SDRAM power-up
sequence can be either a read or a write. This transfer occurs when the
SDRAM power-up sequence has completed. This initial transfer takes
many cycles to complete since the SDRAM power-up sequence must take
place.
SDC Commands
This section provides a description of each of the commands that the SDC
uses to manage the SDRAM interface. These commands are handled auto-
matically by the SDC. A summary of the various commands used by the
on-chip controller for the SDRAM interface follows and is shown in
Table 3-26 on page 3-72.
• Load mode register—initializes the SDRAM operation parameters
during the power-up sequence.
• Single precharge—closes a specific internal bank depending on user
code (ADSP-2137x processors only).
• Precharge all—closes all internal banks, preceding any auto-refresh
command.
• Activate—activates a page in the required internal SDRAM bank
• Read/write
• Auto-refresh—causes the SDRAM to execute an internal CAS
before RAS refresh.
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