SDRAM Controller
3-62 ADSP-21368 SHARC Processor Hardware Reference
In order to set up the SDC and start the SDRAM power-up sequence for
the SDRAMs, use the following procedure. Note that the registers must be
programmed in order.
1. External port control (
EPCTL) register (assign external banks to
SDC)
2. Refresh rate control (SDRRC) register (program refresh counter)
3. SDRAM control (SDCTL) register (define global control for SDC
and SDRAM based on speed and SDRAM specs)
4. Access to SDRAM address space (initiates power-up sequence)
The SDRS bit (bit 3) of the SDRAM control status register can be checked
to determine the current state of the SDC. If this bit is set, the SDRAM
power-up sequence has not been initiated.
In order to set up the SDC and start the SDRAM power-up sequence for
the SDRAMs, the SDRAM refresh rate control register (SDRRC) and
SDRAM memory control register (SDCTL) must be written, and a transfer
must be started to SDRAM address space. The SDRS bit of the SDRAM
control status register can be checked to determine the current state of the
SDC. If this bit is set, the SDRAM power-up sequence has not been
initiated.
The RDIV field of the SDRRC register ia written to set the SDRAM refresh
rate.
Write to the
SDCTL register in order to:
• Set the SDRAM cycle timing options—SDCL, SDTRAS, SDTRP,
SDTRCD, SDTWR, SDBUF
• Enable the SDRAM clock (DSDCTL)
• Set the data path width (X16DE)
To Next Page
Loading...
Need help?
General
