ADSP-21368 SHARC Processor Hardware Reference 12-1
12 TWO WIRE INTERFACE
CONTROLLER
The two wire interface (TWI) controller allows a device to interface to an
inter-IC bus as specified by the Philips I
2
C Bus Specification version 2.1
dated January 2000.
Overview
The TWI is fully compatible with the widely used I
2
C bus standard. It
was designed with a high level of functionality and is compatible with
multimaster, multislave bus configurations. To preserve processor band-
width, the TWI controller can be set up and a transfer initiated with
interrupts only. This allows the processor to service FIFO buffer data
reads and writes. Protocol-related interrupts are optional.
The TWI moves 8-bit data externally while maintaining compliance with
the I
2
C bus protocol. The TWI controller includes the following features.
• Simultaneous master and slave operation on multiple device
systems
• Support for multimaster data arbitration
• 7-bit addressing
• 100K bits/second and 400K bits/second data rates
• General call address support
• Master clock synchronization and support for clock low extension
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