SPORT Programming Examples
5-82 ADSP-21368 SHARC Processor Hardware Reference
To avoid hanging the processor core, check the buffer’s full/empty status
when the processor core’s program reads a word from a SPORT’s receive
buffer or writes a word to its transmit buffer. The full/empty status can be
read in the
DXS bits of the SPCTLx registers. Reading from an empty receive
buffer or writing to a full transmit buffer causes the processor to hang,
while it waits for the status to change.
L
To support debugging buffer transfers, the processor has a buffer
hang disable (BHD) bit. When set (= 1), this bit prevents the proces-
sor core from detecting a buffer-related stall condition, permitting
debugging of this type of stall condition. For more information, see
the BHD bit discussion on on page 5-64.
Multiple interrupts can occur if both SPORTs transmit or receive data in
the same cycle. Any interrupt can be masked in the IMASK register; if the
interrupt is later enabled in the LIRPTL register, the corresponding inter-
rupt latch bit in the IRPTL or LIRPTL registers must be cleared in case the
interrupt has occurred in the same time period.
When SPORT data packing is enabled (PACK = 1 in the SPCTLx control
registers), the transmit and receive interrupts are generated for 32-bit
packed words, not for each 16-bit word.
SPORT Programming Examples
This section provides three programming examples written for the
ADSP-21367/8/9 and ADSP-2137x processors. The first, Listing 5-1,
transmits a buffer of data from
SPORT5 to SPORT4 using DMA and the
internal loopback feature of the SPORT. In this example,
SPORT5 drives
the clock and frame sync, and the buffer is transferred only one time.
The second listing, Listing 5-2, transmits a buffer of data from
SPORT2 to
SPORT3 using direct core reads and writes and the internal loopback feature
of the SPORT. In this example, SPORT2 drives the clock and frame sync,
and the buffer is transferred only one time.
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