SPORT Control Registers and Data Buffers
5-64 ADSP-21368 SHARC Processor Hardware Reference
Frame sync both enable.
SPCTLx registers, bit 22 (FS_BOTH). This bit
applies when the SPORTs channels A and B are configured to trans-
mit/receive data. If set (= 1), this bit issues frame sync only when data is
present in both transmit buffers, TXA and TXB. If cleared (= 0), a frame sync
is issued if data is present in either transmit buffers. This bit applies to
DSP standard serial mode only.
When a SPORT is configured as a receiver, if FS_BOTH is set (= 1), frame
sync is issued only when both the Rx FIFOs (RXSPA and RXSPB) are not
full.
This bit is not used for I
2
S and left-justified sample pair modes. If only
channel A or channel B is selected, the frame sync behaves as if FS_BOTH is
cleared (= 0). If both A and B channels are selected, the word select acts as
if FS_BOTH is set (= 1).
Buffer hang disable. SPCTLx registers, bit 23 (BHD). When cleared (= 0),
this bit causes the processor core to hang when it attempts to write to a
full buffer or read from an empty buffer. When set (= 1), this bit disables
the core hang. In this case, a core read from an empty receive buffer
returns previously read (invalid) data and core writes to a full transmit
buffer to overwrite (valid) data that has not yet been transmitted. This bit
is used in all modes.
Data direction control. SPCTLx registers, bit 25 (SPTRAN). This bit controls
the data direction of the SPORT channel A and B signals.
When cleared (= 0), the SPORT is configured to receive on both channels
A and B. When configured to receive, the RXSPxA and RXSPxB buffers are
activated, while the receive shift registers are controlled by
SPORTx_CLK
and SPORTx_FS. The TXSPxA and TXSPxB buffers are inactive.
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