ADSP-21368 SHARC Processor Hardware Reference 5-59
Serial Ports
Serial Port Control Registers (SPCTLx)
The main control registers for each SPORT are the SPORT control regis-
ters, SPCTLx. These registers are described in “SPORT Serial Control
Registers (SPCTLx)” on page A-29. When changing operating modes,
clear the SPORT control registers before the new mode is written to the
registers.
There is one global control and status register for each SPORT (unlike
previous SHARC designs where SPORTs were paired) for multichannel
operation. These registers are SPMCTL0–7 and they define the number of
channels, provide the status of the current channel, enable multichannel
operation, and set the multichannel frame delay. These registers are
described in “SPORT Multichannel Control Registers (SPMCTLx)” on
page A-40.
The SPCTLx registers control the operating modes of the SPORTs for the
I/O processor. Table 5-9 lists all the bits in the SPCTLx registers.
Table 5-9. SPCTLx Control Bit Comparison in Four SPORT Operation
Modes
Bit Standard DSP Serial Mode Left-justified and I
2
S Mode Multichannel Mode
0 SPEN_A SPEN_A Reserved
1 DTYPE Reserved DTYPE
2 DTYPE Reserved DTYPE
3 LSBF Reserved LSBF
4 SLEN0 SLEN0 SLEN0
5 SLEN1 SLEN1 SLEN1
6 SLEN2 SLEN2 SLEN2
7 SLEN3 SLEN3 SLEN3
8 SLEN4 SLEN4 SLEN4
9 PACK PACK PACK
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