SPORT Control Registers and Data Buffers
5-60 ADSP-21368 SHARC Processor Hardware Reference
10 ICLK MSTR ICLK
11 OPMODE OPMODE OPMODE
12 CKRE Reserved CKRE
13 FSR Reserved Reserved
14 IFS Reserved IMFS
15 DIFS DIFS Reserved
16 LFS FRFS LMFS
17 LAFS LAFS Reserved
18 SDEN_A SDEN_A SDEN_A
19 SCHEN_A SCHEN_A SCHEN_A
20 SDEN_B SDEN_B SDEN_B
21 SCHEN_B SCHEN_B SCHEN_B
22 FS_BOTH No effect Reserved
23 BHD BHD BHD
24 SPEN_B SPEN_B Reserved
25 SPTRAN SPTRAN SPTRAN
26 ROVF_B, or TUVF_B ROVF_B, or TUVF_B DERR_B, ROVF_B, or
TUVF_B
27 DXS_B DXS_B DXS_B
28 DXS_B DXS_B DXS_B
29 ROVF_A, or TUVF_A ROVF_A, or TUVF_A DERR_A, ROVF_A, or
TUVF_A
30 DXS_A DXS_A DXS_A
31 DXS_A DXS_A DXS_A
Table 5-9. SPCTLx Control Bit Comparison in Four SPORT Operation
Modes (Cont’d)
Bit Standard DSP Serial Mode Left-justified and I
2
S Mode Multichannel Mode
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