ADSP-21368 SHARC Processor Hardware Reference 8-3
Pulse Width Modulation
of period, it is equal to period ÷ 2 (rounded up). Therefore, for a duty
value programmed in two’s-complement, the PWM pulse width is given
by:
To generate constant logic high on PWM output, program the duty regis-
ter with the value ≥ + period ÷ 2.
To generate constant logic low on PWM output, program the duty regis-
ter with the value ≥ – period ÷ 2.
For example, using an odd period of p = 2n + 1, the counter within the
PWM generator counts as (–n...0...+n). If the period is even (p = 2n), then
the counter counts as (–n+1...0...n).
For more information, see “PWM Channel Duty Control Registers
(PWMAx, PWMBx)” on page A-84.
Center-Aligned Mode
Most of the following description applies to paired mode, but it can also
be applied to non-paired mode, the difference being that each of the four
outputs from a PWM group is independent. Within center-aligned mode,
there are several options to choose from.
Center-aligned single update mode. Duty cycle values are programmable
only once per PWM period, so the resultant PWM patterns are symmetri-
cal about the midpoint of the PWM period.
Center-aligned, double-update mode. Duty cycle values are programma-
ble only twice per PWM period. This second updating of the PWM
registers is implemented at the midpoint of the PWM period, producing
asymmetrical PWM patterns that produce lower harmonic distortion in
three-phase PWM inverters.
Width period()2÷ duty+=
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