ADSP-21368 SHARC Processor Hardware Reference 13-3
Precision Clock Generators
being a clock and frame sync slave. The clock generated by the SPORT is
sufficient for most of the serial communications, but it is suboptimal for
analog/digital conversion. Therefore, all precision data converters should
be synchronized to a clock generated by the PCG or to a clean (low jitter)
clock that is fed into SRU1 off-chip through a pin.
L
Any clock or frame sync unit should be disabled (have its enable bit
cleared) before changing any of the associated parameters.
Clock Outputs
Each of the four units (A, B, C, and D) produces a clock output and a
frame sync output. The clock output is derived from the input to the PCG
with a 20-bit divisor as shown in the following equation.
If the divisor is zero or one, the PCG’s clock generation unit is bypassed,
and the clock input is connected directly to the clock output. Otherwise,
the PCG unit clock output frequency is equal to the input clock fre-
quency, divided by a 20-bit integer. This integer is specified in bits 19–0
of the
PCG_CTLx1 registers for units A, B, C and D respectively. These reg-
isters and bits are also described in Table A-63 on page A-156 and
Table A-64 on page A-157.
The clock outputs have four other control bits that enable the A, B, C,
and D units, ENCLKA, ENCLKB, ENCLKC, and ENCLKD respectively (bits 31 of
the PCG_CTLx0 registers). These bits enable (= 1) and disable (= 0) the
clock output signal for units A, B, C, and D respectively. When disabled,
clock output is held at logic low.
Frequency of Clock Output =
Frequency of Clock Input
Clock Divisor
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