Analog Devices SHARC ADSP-21368 - Load Mode Register

SDRAM Controller
3-64 ADSP-21368 SHARC Processor Hardware Reference
• Self-refresh entry—places the SDRAM in self-refresh mode, in
which the SDRAM powers down and controls its refresh opera-
tions internally.
• Self-refresh exit—exits from self-refresh mode by expecting
auto-refresh commands from SDC.
• NOP/command inhibit—no operation used to insert wait states
for activate and precharge cycles
• Burst Stop command—used to interrupt any full page burst opera-
tion (ADSP-2137x processors only).
Load Mode Register
This command is initializes SDRAM operation parameters. It is a part of
the SDRAM power-up sequence. Load mode register uses the address bus
of the SDRAM as data input. The power-up sequence is initiated by writ-
ing 1 to the
SDPSS bit in the SDCTL register and then writing or reading
from any enabled address within the SDRAM address space to trigger the
power-up sequence. The exact order of the power-up sequence is deter-
mined by the SDPM bit of the SDCTL register.
The load mode register command initializes the following parameters.
• Burst length = 1, bits 2–0, always zero
• Optional burst length = full page, bits 2–0, all ones (ADSP-2137x
processors only).
• Wrap type = sequential, bit 3, always zero
• Ltmode = latency mode (CAS latency), bits 6–4, programmable in
the
SDCTL register
• Bits 14–7, always zero