ADSP-21368 SHARC Processor Hardware Reference 5-23
Serial Ports
Enabling SPORT Master Mode (MSTR)
The SPORTs transmit and receive channels can be configured for master
or slave mode. In master mode, the processor generates the word select
and serial clock signals for the transmitter or receiver. In slave mode, an
external source generates the word select and serial clock signals for the
transmitter or receiver. When
MSTR is cleared (=0), the processor uses an
external word select and clock source and the SPORT transmitter or
receiver is a slave. When MSTR is set (=1), the processor uses the processor’s
internal clock for word select and clock source and the SPORT transmit-
ter or receiver is the master. For more information, see “Setting the
Internal Serial Clock and Frame Sync Rates” on page 5-17.
Selecting Transmit and Receive Channel Order (FRFS)
In master and slave modes, programs can configure which I
2
S channel that
each SPORT channel transmits or receives first. By default, the SPORT
channels transmit and receive on the right I
2
S channel first. The left and
right I
2
S channels are time-duplexed data channels.
To select the channel order, set the FRFS bit (= 1) to transmit or receive on
the left channel first, or clear the FRFS bit (= 0) to transmit or receive on
the right channel first.
Selecting Frame Sync Options (DIFS)
The
DIFS bit selects whether the serial port uses the data independent
frame sync or the data dependant frame sync. Normally, the internally
generated frame sync signal is output only when the transmit buffer has
data ready to transmit for the transmitter and when the receive buffer is
not full for the receiver. The data-independent frame sync (DIFS) mode
allows the continuous generation of the
FSx signal, with or without new
data in the transmit register or the receive buffer.
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