ADSP-21368 SHARC Processor Hardware Reference 6-35
Serial Peripheral Interface Ports
• See “Interrupt Registers” on page B-6 for
IRPTL and LIRPTL register
bit descriptions.
• See “SPI DMA Configuration Registers (SPIDMAC, SPID-
MACB)” on page A-62 for SPIDMAC register bit descriptions.
Error Signals and Flags
This section describes the error signals and flags that determine the cause
of transmission errors for an SPI port. The bits MME, TUNF, and ROVF are set
in the SPISTAT register when a transmission error occurs. Corresponding
bits (SPIMME, SPIUNF, and SPIOVF) in the SPIDMAC register are set when an
error occurs during a DMA transfer. These W1C bits generate an SPI
interrupt when any one of them are set.
• See “SPI Port Status (SPISTAT, SPISTATB) Registers” on
page A-56 for more information about the SPISTAT register bits.
• See “SPI DMA Configuration Registers (SPIDMAC, SPID-
MACB)” on page A-62 for more information about the SPIDMAC
register bits.
Mode Fault Error (MME)
The MME bit is set in the SPISTAT register when the SPIDS input pin of a
device that is enabled as a master is driven low by some other device in the
system. This occurs in multimaster systems when another device is also
trying to be the master.
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