SPI Interrupts
6-34 ADSP-21368 SHARC Processor Hardware Reference
During IOP-driven transfers (DMA), an SPI interrupt is triggered:
3. At the completion of a single DMA transfer,
4. At the completion of a number of DMA sequences (if DMA chain-
ing is enabled),
5. When a DMA error has occurred.
Again, the
SPIDMAC register must be initialized properly to enable DMA
interrupts.
Each of these five interrupts are serviced using the interrupt associated
with the module being used. The primary SPI uses the SPIHI (programma-
ble interrupt 1 by default, 0x90030) interrupt and the secondary SPI uses
the SPILI (programmable interrupt 18 by default, 0x90074) interrupt.
Whenever an SPI interrupt occurs (regardless of the cause), the SPILI or
SPIHI interrupts are latched. To service the primary SPI port, unmask (set
= 1) the SPIHI bit (bit 12) in the IMASK register. To service the secondary
SPI port, unmask (set = 1) the SPILIMSK bit (bit 19) in the LIRPTL register.
For a list of these bits, see Table 2-3 on page 2-9 and “LIRPTL Register
Bit Descriptions” on page B-8.
To globally enable interrupts, set (= 1) the IRPTEN bit in the MODE1 register.
When using DMA transfers, programs must also specify whether to gener-
ate interrupts based on transfer or error status. For DMA transfer status
based interrupts, set the
INTEN bit in the SPIDMAC register; otherwise, set
the INTERR bit to trigger the interrupt if one of the error conditions occurs
during the transmission like multimaster error (
MME), transmit buffer
underflow (TUNF – only if SPIRCV = 0), or receive buffer overflow (ROVF –
only if
SPIRCV = 1). During core-driven transfers, the TUNF and ROVF error
conditions do not generate interrupts.
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