Analog Devices SHARC ADSP-21368 User Manual

Shared Memory Interface
3-94 ADSP-21368 SHARC Processor Hardware Reference
Shared Memory and the SDRAM Controller
In a shared memory environment, the SDRAM is shared among two or
more ADSP-21368 processors. SDRAM input signals (including clock)
are always driven by the bus master. The current bus master continues to
hold the bus for t
RASmin
– 1 cycles before giving up the bus to the new bus
master.
The clock is three-stated on releasing the bus, and command lines are
driven for one extra cycle with a NOP instruction. The new bus master also
drives a NOP on the command lines immediately after acquiring the bus
mastership. This prevents latching of invalid commands due to glitches on
the clock, (if any) during bus mastership changeover.
The following should be noted when using the SDRAM controller in a
shared memory system.
1. Processors do not track commands on the bus.
2. The master processor issues a refresh command immediately after
getting bus-mastership and clearing its refresh counter. This sim-
plifies the design and avoids maintaining the refresh counters in
sync on all processors using an overhead of a few clock cycles on
each mastership changeover.
3. For shared SDRAM timing, all processors must have the same
SDCLK frequency, and the same core clock (CCLK) to SDRAM clock
(SDCLK) ratio. This implies that all processors must use the same
settings in their respective control (
SDCTL) and refresh rate (SDRRC)
registers.
Shared Memory Booting
The ADSP-21368 processor allows booting for multiple processors from a
single EPROM/FLASH. For more information, see “Shared Memory
Booting” on page 14-40.

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP