ADSP-21368 SHARC Processor Hardware Reference A-69
Register Reference
Input Data Port FIFO Register (IDP_FIFO)
This register (shown in Figure A-29) provides information about the out-
put of the IDP FIFO. Normally, IDP_FIFO is used only to read and remove
the top sample from the FIFO. However, the core may also write to this
register. When it does so, the audio data word is pushed into the input
side of the FIFO as if it had come from the SRU on the channel encoded
in the three LSBs. This can be useful for verifying the operation of the
FIFO, the DMA channels, and the status portions of the IDP. The IDP
FIFO is an 8-deep FIFO.
Channel-encoding provides for eight combinations, corresponding to the
eight inputs. This register format applies when using channels 1–7 and
also when using Channel 0 in serial mode. When using channel 0 in paral-
lel mode, refer to the description of the four possible packing modes. For
more information, see “Packing Unit” on page 7-9.
L
The information in Table A-18 is not valid when data comes from
the PDAP channel.
Figure A-29. IDP_FIFO Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Serial Input Data
Indicates serial input
port channel number
IDP Channel Encoding
Bits
Left/Right channel as specified by
frame sync
LR_STAT
IDP_FIFO (0x24D0)
Serial Input Data
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