ADSP-21368 SHARC Processor Hardware Reference 3-93
External Port
While the
BUSLK bit is set, the processor can determine if it has acquired
bus mastership by executing a conditional instruction with the bus master
(BM) or not bus master (Not BM) condition codes, for example:
IF NOT BM JUMP(PC,0); /* Wait for bus mastership */
If the processor becomes the bus master, it can proceed with the external
read or write. If not, it can clear its BUSLK bit and try again later.
A read-modify-write operation is accomplished with the following steps:
1. Request bus lock by setting the BUSLK bit in SYSCTL.
2. Wait for bus mastership to be acquired.
3. Read the semaphore, test it, then write to it.
Locking the bus prevents other processors from writing to the semaphore
while the read-modify-write operation is occurring.
Shared Memory Interface Status
The system status (SYSTAT) register provides status information for host
and multiprocessor systems. Table 3-32 shows the status bits in this
register.
Table 3-32. SYSTAT Register
Bit(s) Name Definition
1BSYNBus Synchronized. This bit indicates whether the proces-
sor’s bus arbitration logic is synchronized (if set, =1) or is
not synchronized (if cleared, =0, reset value).
6-4 CRBM Current Bus Master. These bits indicate the ID of the
processor that is currently the bus master in a multipro-
cessor system.
10-8 IDC ID Code. These bits indicate the state of the ID pins on
the processor.
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