ADSP-21368 SHARC Processor Hardware Reference 13-7
Precision Clock Generators
Frame Sync Output Synchronization With
an External Clock
The frame sync output may be synchronized with an external clock by
programming the PCG_SYNC and PCG_SYNC2 registers (shown in
Figure A-77 on page A-160) and the PCG control registers (PCG_CTLA0–1,
PCG_CTLB0–1, PCG_CTLC0–1, and PCG_CTLD0–1) appropriately. In this mode,
the rising edge of the external clock is aligned with that of the frame sync
output (shown in Figure 13-2). The external clock is routed to the PCG
block from any of the SRU1 group A source signals through the SRU_CLK4
and SRU_CLK5 registers (described in Table 4-4 on page 4-23).
The synchronization with the external clock is enabled by setting bits 0
and 16 of the PCG_SYNC register for frame sync A or B and the PCG_SYNC2
register for C or D output. The phase must be programmed to 3, so that
the rising edge of the external clock is in sync with the frame sync.
Programming should occur in the following order.
1. Program the PCG_SYNC and PCG_SYNC2 and the PCG_CTLA0–1,
PCG_CTLB0–1, PCG_CTLC0–1, and PCG_CTLD0–1 registers
appropriately.
2. Enable clock or frame sync, or both.
Since the rising edge of the external clock is used to synchronize with the
frame sync, the frame sync output is not generated until a rising edge of
the external clock is sensed.
The clock output cannot be aligned with the rising edge of the external
clock as there is no phase programmability. Once CLKA through CLKD have
been enabled (by programming bit 1 and bit 17 of the
PCG_SYNC register
for CLKA and CLKB respectively and, bit 1 and 17 of PCG_SYNC2 register for
CLKC and CLKD respectively) these outputs are activated when a low-to-high
transition is sensed in the external clock (
MISCA4_I, MISCA5_I).
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