ADSP-21368 SHARC Processor Hardware Reference 7-27
Input Data Port
DAI_IRPTL_L register. Reading these DAI shadow registers
(DAI_IRPTL_H_SH and DAI_IRPTL_L_SH) does not destroy the con-
tents of the DAI_IRPTL_H and DAI_IRPTL_L registers.
• The IDP can run both simple and ping-pong DMAs in different
channels. When running simple DMA, initialize the corresponding
IDP_DMA_Ix, IDP_DMA_Mx, and IDP_DMA_Mx registers. When running
ping-pong DMA, initialize the corresponding IDP_DMA_AIx,
IDP_DMA_BIx, IDP_DMA_Mx, and IDP_DMA_PCx registers.
• A new feature of dropping DMA requests from the FIFO has been
added. If one channel has finished its DMA, but the IDP_DMA_EN
bit is still high, any data corresponding to that channel is skipped
by the DMA controller. This feature is provided to avoid stalling
the DMA of other channels, which are still in an active DMA state.
To avoid this data loss, programs can toggle IDP_DMA_EN low.
• Disabling IDP DMA by resetting the IDP_DMA_EN bit requires 1
HCLK cycle. Disabling an individual channel DMA by resetting the
IDP_DMA_ENx bits requires 2 HCLK cycles.
DMA Channel Parameter Registers
The eight DMA channels each have two sets of registers for simple and
ping-pong DMA. For simple DMA, an I-register (index pointer, 19 bits),
an M-register (modifier/stride, 6 bits), and a C-register (count, 16 bits)
are used. For ping-pong DMA, A and B index registers (AI/BI register
pointer, 19 bits) and a PC register (DMA count, 16 bits) are used, along
with the M-register.
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