FIFO to Memory Data Transfer
7-26 ADSP-21368 SHARC Processor Hardware Reference
When an overflow occurs, incoming data from IDP channels is not
accepted into the FIFO, and data values are lost. New data is only
accepted once space is again created in the FIFO.
• For serial input channels, data is received in an alternating fashion
from left and right channels. Data is not pushed into the FIFO as a
full left/right frame. Rather, data is transferred as alternating
left/right words as it is received. For the PDAP and 32-bit
(non-audio) serial input, data is transferred as packed 32-bit words.
• The state of all eight DMA channels is reflected in the
IDP_DMAx_STAT bits (bits 24–17 of DAI_STAT register). These bits
are set once the IDP_DMA_EN bit and IDP_DMA_ENx bits are set, and
remain set until the last data from that channel is transferred. Even
if IDP_DMA_EN bit and IDP_DMA_ENx bits remain set, this bit clears
once the required number of data transfers takes place. For more
information, see “DAI Pin Buffer Status Register
(DAI_PIN_STAT)” on page A-112.
L
Note that when a DMA channel is not used (that is, parameter reg-
isters are at their default values) that DMA channel’s
corresponding IDP_DMAx_STAT bit is set (= 1).
• The three LSBs of data from the serial inputs are channel encoding
bits. Since the data is placed into a separate buffer for each channel,
these bits are not required and are set to low when transferring data
to internal memory through the DMA. Bit 3 still contains the
left/right status information. In the case of PDAP data or 32-bit
I
2
S and left-justified modes, these three bits are part of the 32-bit
data.
• An interrupt is generated at the end of a DMA, which is cleared by
reading the DAI_IRPTL_H or DAI_IRPTL_L registers.
• A read of the DAI_IRPTL_H_SH register provides the same data as a
read of the
DAI_IRPTL_H register. Likewise, a read of the
DAI_IRPTL_L_SH register provides the same data as a read of the
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