Clock Derivation
14-16 ADSP-21368 SHARC Processor Hardware Reference
When the PLL is programmed using a multiplier and a divisor, the
DIVEN
and PLLBP bits should NOT be programmed in the same core clock cycle.
There should be a delay of at least one core clock cycle between program-
ming these bits. The approaches described below and shown in
Listing 14-3, Listing 14-4 and Listing 14-5 can be used to accomplish
this.
PLL Programming Examples
Use the following procedure to program the PLL. Please include the corre-
sponding processor-specific header definition files def21367.h,
def21368.h, def21369.h, def21371.h, def21375.h and cdef21367.h,
cdef21368.h, cdef21369.h, cdef21371.h, and cdef21375.h, which contain
the register and bit definitions.
1. Set the PLL multiplier and divisor value and enable the divisor by
setting the DIVEN bit.
2. After one core clock cycle, place the PLL in bypass mode by setting
(= 1) the PLLBP bit.
3. Wait in bypass mode until the PLL locks.
4. Take the PLL out of bypass mode by clearing (= 0) the bypass bit.
Listing 14-3. PLL Programming Example 1
ustat2 = dm(PMCTL);
bit clr ustat2 PLLM63|PLLD8; /* clear old multiplier and
divisor*/
bit set ustat2 DIVEN | PLLD4 |PLLM16; /* set a multiplier of
16 and a divider of 4 */
dm(PMCTL) = ustat2;
bit set ustat2 PLLBP; /* Put PLL in bypass mode. */
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