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Input Data Port Registers

A-72 ADSP-21368 SHARC Processor Hardware Reference

Input Data Port Ping-Pong DMA Registers

Each of the eight DMA channels have an index register with an index

pointer (19 bits) and a counter register with a count (16 bits) that are used

when performing ping-pong DMA. For example, IDP_DMA_I1A and

IDP_DMA_PC1 control ping-pong DMA for IDP channel 1. The following

sections describe these registers.

IDP Ping-Pong Index Registers (IDP_DMA_IxA)

Table A-22 provides information about the IDP ping-pong DMA index

registers.

IDP_DMA_C3 0x2423 0x00000 IDP channel 3 DMA count register

IDP_DMA_C4 0x2424 0x00000 IDP channel 4 DMA count register

IDP_DMA_C5 0x2425 0x00000 IDP channel 5 DMA count register

IDP_DMA_C6 0x2426 0x00000 IDP channel 6 DMA count register

IDP_DMA_C7 0x2427 0x00000 IDP channel 7 DMA count register

Table A-22. IDP_DMA_IxA Registers

IDP_DMA_I0A 0x2408 0x00000 IDP channel 0 index A ping-pong DMA register

IDP_DMA_I1A 0x2409 0x00000 IDP channel 1 index A ping-pong DMA register

IDP_DMA_I2A 0x240A 0x00000 IDP channel 3 index A ping-pong DMA register

IDP_DMA_I3A 0x240B 0x00000 IDP channel 4 index A ping-pong DMA register

IDP_DMA_I4A 0x240C 0x00000 IDP channel 4 index A ping-pong DMA register

IDP_DMA_I5A 0x240D 0x00000 IDP channel 5 index A ping-pong DMA register

IDP_DMA_I6A 0x240E 0x00000 IDP channel 6 index A ping-pong DMA register

Table A-21. IDP_DMA_Cx Registers (Cont’d)

Analog Devices SHARC ADSP-21368 User Manual

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