ADSP-21368 SHARC Processor Hardware Reference 5-73
Serial Ports
SPORT interrupts occur on the second system clock (
CLKIN) after the last
bit of the serial word is latched in or driven out.
Moving Data Between SPORTs and
Internal Memory
Transmit and receive data can be transferred between the SPORTs and
on-chip memory with single word transfers or with DMA block transfers.
Both methods are interrupt-driven, and use the same internally-generated
interrupts.
SPORT DMA provides a mechanism for receiving or transmitting an
entire block of serial data before the interrupt is generated. When SPORT
DMA is not enabled, the SPORT generates an interrupt every time it
receives or starts to transmit a data word. The processor’s on-chip DMA
controller handles the DMA transfer, allowing the processor core to
continue running until the entire block of data is transmitted or received.
Service routines can then operate on the block of data rather than on sin-
gle words, significantly reducing overhead.
DMA Block Transfers
The DSP’s on-chip DMA controller allows automatic DMA transfers
between internal memory and each of the two channels of each SPORT.
Each SPORT has two channels for transferring data, and each can be con-
figured to receive or to transmit. There are twelve DMA channels for
SPORT operations. The SPORT DMA channels are numbered as shown
in Table 5-11.
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