ADSP-21368 SHARC Processor Hardware Reference 5-81
Serial Ports
Therefore, set the direction bit, the SPORT enable bit, and DMA enable
bits before initiating any operations on the SPORT data buffers. If the
processor operates on the inactive transmit or receive buffers while the
SPORT is enabled, it can cause unpredictable results.
SPORT DMA Chaining
In chained DMA operations, the processor’s DMA controller automati-
cally sets up another DMA transfer when the contents of the current
buffer are transmitted (or received). The chain pointer registers (
CPSPxy)
function as a pointer to the next set of buffer parameters stored in mem-
ory. The DMA controller automatically downloads these buffer
parameters to set up the next DMA sequence. For more information on
SPORT DMA chaining, see “Setting Up DMA Parameter Registers” on
page 2-24.
DMA chaining occurs independently for the transmit and receive channels
of each SPORT. Each SPORT DMA channel has a chaining enable bit
(SCHEN_A or SCHEN_B) that when set (= 1) enables DMA chaining and
when cleared (= 0) disables DMA chaining. Writing all zeros to the
address field of the chain pointer registers (CPSPxy) also disables chaining.
Single Word Transfers
Individual data words may also be transmitted and received by the
SPORTs, with interrupts occurring as each 32-bit word is transmitted or
received. When a SPORT is enabled and DMA is disabled, the SPORT
interrupts are generated whenever a complete 32-bit word has been
received in the receive buffer, or whenever the transmit buffer is not full.
Note that both channel A and B buffers share the same interrupt vector.
Single word interrupts can be used to implement interrupt-driven I/O on
the SPORTs.
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