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Analog Devices SHARC ADSP-21368

Analog Devices SHARC ADSP-21368
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SPORT Operation Modes
5-16 ADSP-21368 SHARC Processor Hardware Reference
Left-Justified Sample Pair Mode
In left-justified sample pair mode, each frame sync cycle receives or trans-
mits two samples of data—one sample on the high segment of the frame
sync, the other on the low segment of the frame sync. Prior to develop-
ment of the I
2
S standard, many manufacturers used a variety of
non-standard stereo modes. Some companies continue to use this mode,
which is supported by many of today’s audio front-end devices.
Programs have control over various attributes of this mode. One attribute
is the number of bits (8- to 32-bit word lengths). However each sample of
the pair that occurs on each frame sync must be the same length. Set the
late frame sync bit (LAFS bit) = 1 for left-justified sample pair mode. (See
Table 5-1 on page 5-11.) Then, choose the frame sync edge associated
with the first word in the frame sync cycle, using the FRFS bit
(1 = frame on falling edge of frame sync, 0 = frame on rising edge of frame
sync).
Refer to Table 5-1 on page 5-11 for additional information about specify-
ing left-justified sample pair mode.
In left-justified sample pair mode, if both transmit channels (TXSPxA and
TXSPxB) on a SPORT are enabled, then the SPORT transmits these chan-
nels simultaneously. In other words, each channel transmits a sample pair.
Data is transmitted in MSB-first format. If both receive channels (RXSPxA
and RXSPxB) on a SPORT are enabled, the SPORT receives
simultaneously.
L
Multichannel operation and companding are not supported in
left-justified sample pair mode.
Each SPORT transmit or receive channel has a buffer enable, DMA
enable, and chaining enable bits in its SPCTLx control register. The
SPORTx_FS signal is used as the transmit and/or receive word select signal.
DMA-driven or interrupt-driven data transfers can also be selected using
bits in the
SPCTLx register.

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