Clock Derivation
14-26 ADSP-21368 SHARC Processor Hardware Reference
Programming The RUNRSTCTL Register
To configure running reset:
1. Set bit 0 (=1) to change
RESETOUT/CLKOUT pin direction to input.
2. Ensure that the RESETOUT/CLKOUT pin is driven to a proper state,
and then assert RUNRSTEN to sensitize logic to the state of the
RESETOUT/CLKOUT pin.
If bit 1 of the RUNRSTCTL register is not set, attempting to cause a
running reset by toggling the RESETOUT/CLKOUT pin does not result
in a reset.
L
The RUNRSTCTL register is reset only on assertion of a hardware
reset, software reset, emulator reset, or by writing to the appropri-
ate bits of the RUNRSTCTL register via software.
The system reacts to the assertion and recognition of a running reset in the
following way.
• The core-PLL is NOT reset, and continues to run
• Internal memory SRAM contents remain unaltered
• The processor core and peripherals are reset exactly as if a
Power-on (hardware) reset is asserted, except:
• The SDRAM controller continues to run and refresh as
programmed.
• The contents of external SDRAM are unaffected, and retain
their values prior to a running reset.
• A system boot is NOT initiated. Instead, the program
counter is cleared and program execution begins from the
very first location of program memory (from the reset inter-
rupt vector table).
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