Analog Devices SHARC ADSP-21368 User Manual

Booting
14-40 ADSP-21368 SHARC Processor Hardware Reference
Shared Memory Booting
To boot multiple processors from a single EPROM/FLASH, the processor
performs the following steps.
1. Arbitrate for the bus.
2. Receive through DMA the 256-word boot kernel, after becoming
bus master.
3. Release the bus, allowing the next processor access to the
EPROM/FLASH.
4. Execute the loaded instructions. These usually consist of the boot
kernel, which brings in the remaining application code.
For more information on developing executables for shared-memory boot-
ing, see the VisualDSP++ Loader Manual or the VisualDSP++ Loader and
Linker Manual (depending on the VisualDSP++ release you are using).
The
MS1 signals from each processor may be wire ORed together to drive
the chip select pin of the EPROM. Each processor boots in turn, accord-
ing to its priority. When the last processor has finished booting, it must
inform the others (which may be in the idle state) that program execution
can begin (if all the processors are to begin executing instructions simulta-
neously). An example system that uses an alternating technique appears in
Figure 14-10. When multiple processors boot from one EPROM, they
can boot either identical code or different code from the EPROM.

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP